1. Field
Embodiments of the inventive concepts relate to a semiconductor device having a repairable penetration electrode. More particularly, embodiments of the inventive concepts relate to a semiconductor device having a repairable penetration electrode, which includes first and second signal transfer regions including main penetration electrodes and a repair region including a spare penetration electrode disposed between the first and second signal transfer regions, and which substitutes the spare penetration electrode of the repair region for a defective main penetration electrode when a defect occurs at the main penetration electrode of the first and second signal transfer regions.
2. Description of the Related Art
In a semiconductor industry, packaging techniques for integrated circuits have been developed to meet the demands for miniaturization and mounting reliability. For example, the demand for the miniaturization accelerates the development of techniques for packages closer to a chip size, and the demand for the mounting reliability highlights the importance of packaging techniques capable of improving the efficiency of mounting operations and mechanical and electrical reliability after the mounting operations.
The term “stack” used in the semiconductor industry means a technique for vertically stacking at least two semiconductor chips or packages. The stack technique can realize a product having a memory capacity greater than a memory capacity realized by a semiconductor integration process. In addition, the stack technique may mean a method for stacking packaged individual semiconductor chips.
Recently, as miniaturization of products, high package density, high performance, and integration demand between chips have continuously increased, three-dimensional (3D) package techniques have been developed. A through silicon via (TSV) technique is an important technique used in 3D packages of silicon devices. Conventional silicon chips have a structure in which electrodes exist only on a surface for external connection. However, a connecting electrode structure is formed to penetrate front and back surfaces of a chip in the TSV technique, and chips having the connecting electrode structures are three-dimensionally stacked.
For example, Korean Patent Publication No. 10-2012-0071921 (Application No. 10-2010-133657) discloses a composition that fills a hole of a through silicon via by using metal powder, solder powder, thermosetting resin, a reducing agent, and a hardening agent.